Low power Pushbutton ON/OFF Controller solution from Linear Technology

 

All of the flexible timing circuitry required to debounce the on/off pushbutton is integrated within the LTC2950. For applications that need additional time during power down, it also provides an adjustable timer.

The LTC2950 can handle a wide range of input power supply because it runs across a broad input voltage range of 2.7V to 26.4V. The LTC2950 is perfectly suited for battery-powered applications due to its extremely low quiescent current (6µA average). The part comes in two versions to support either positive or negative enable polarities. 

The turn-on time can be adjusted by placing an external capacitor on the ONT pin and the turn-off time on the OFFT pin. Open-drain interrupt output INT pin triggers after the pushbutton turn-off event is detected. LTC2950 interrupts the system (µP) by bringing the INT pin low. Once the system finishes its power-down and housekeeping tasks, it sets KILL low, which in turn releases the enable output. If at the end of the power-down timer (1024ms) KILL is still high, the enable output is released immediately.

Power ON/OFF Control with Push button (Ref: TI Application Report)

 

This simple push-button circuit allows a system to turn on with a short button press and turn off when the button is held down. Essentially, the circuit employs D-type flip-flops with asynchronous clear (U2), inverting (U3), and non-inverting (U1) Schmitt-Trigger buffers.

At the initial state, CLR is set to HIGH, U2's clear data input is HIGH and output Q (POWER ENABLE ) is at Q0, which is latched into the last state as Pin D transferred to the output Pin Q is waiting for CLK rising edge.

To set the output Q, POWER ENABLE HIGH, press the button, B1 which forces the PB signal to go LOW and the CLK signal to go HIGH as U3 inverts the logic and causing the CLK rising edge. At the same time, The CLR signal starts to go LOW, but because the R1 resistor and C1 capacitor create an RC delay, which causes the CLR signal to decay slowly.  With this short button press, the CLR signal does not go LOW, which allows for the output Q, POWER ENABLE signal to go HIGH with input D is tied to HIGH.  The POWER ENABLE signal remains HIGH even if the button is pressed again after the initial press.

The power-off process begins with holding down the button for an extended period of time. The button must be held for longer than the RC delay specified by R1 and C1. When the button is pressed long enough, the CLR signal goes LOW enough to meet the conditions for the asynchronous clear to occur, causing the POWER ENABLE signal to be low. 

Furthermore, D1 is present within the RC circuit, allowing the short time between turnoff and turn-on to bypass R1 and rapidly charge C1. 

The delay time can be adjusted using different values for C1 as below.

DC Ground to Earth Connection in PCB design

 In electronics, "earth ground" refers to a direct connection to the Earth, which is a safety connection to the physical earth, often via the chassis. This connection is primarily designed to provide a stable reference voltage rather than to carry current during normal operation.

Under typical conditions, it shouldn't conduct current when devices are drawing power. Instead, it only comes into play to safely dissipate unwanted currents, such as electromagnetic interference (EMI) or electrostatic discharge (ESD) events. Essentially, think of the earth's ground as a safety net that helps manage electrical noise and protect sensitive equipment.

The standard method for connecting DC ground to Earth involves the use of a resistor-capacitor (RC) network, as illustrated below. A capacitor with sufficient capacitance is employed to effectively couple the two points for the attenuation of high-frequency noise. In parallel with this capacitor, a high-value resistor, typically around 1 megohm, is utilized to ensure that the DC ground does not float, thereby maintaining a stable reference potential. This configuration allows for effective noise suppression while preserving the integrity of the DC ground.

What is Encroached Vias?

The encroached via concept is one that uses soldermask on the bottom via pad without filling the via’s plated-through hole. Encroachment-type vias have the top-side soldermask open and the bottom-side soldermask opening adjusted, so that it is slightly larger than the via hole size (typically +0.06 mm).

If the mask is opened all the way around an EPAD via (OPEN via), then solder can flow out from under the QFN EPAD onto the bottom-side via pad as a big drop. This drop often drips off during the motion of the unit through the reflow oven, pulling solder from the EPAD joint. This solder “scavenging” can render the EPAD connection unreliable and/or cause the device to tilt, resulting in unreliable pin connections.

Encroached via can be created in Altium Design by defining Solder Mask Expansion setting with negative values as below. For best result, via with and Finished hole size, FHS of 0.25 to 0.3mm and bottom-side soldermask opening of 0.055 mm to 0.075mm larger than the FHS.

Ultra-Precise, Current-Sense Amplifier

 

The INAx290 is an ultra-precise, current-sense amplifier that can measure voltage drops across shunt resistors over a wide common-mode range from 2.7 V to 120 V. Depending on your application, different gains can be selected.

 – A1 devices: 20 V/V

 – A2 devices: 50 V/V 

– A3 devices: 100 V/V 

– A4 devices: 200 V/V 

– A5 devices: 500 V/V 

Using Simple Hall-effect Sesnor as a position Sensor

 

The AH1806 is a high-sensitivity, micro-power Omnipolar Hall effect switch IC, designed for portable and battery powered consumer to home appliance and industrial applications such as smart-meter magnetic tamper detection

Schmitt trigger for cleaning up noisy or slow-rising digital signals

 

A Schmitt trigger is a circuit that converts an analog input signal into a digital output signal with hysteresis. It's characterised by two different threshold voltages, one for the rising input signal and another for the falling input signal, which provides noise immunity and prevents oscillations.

Designing Thermal Vias

Enhancing thermal transfer for FR-4 PCBs can be achieved cost-effectively by incorporating thermal vias and plated through-holes (PTH) between conductive layers. These methods efficiently dissipate heat and improve the overall performance of the PCB.

Key design considerations for vias include:

- Adhering to the manufacturer's recommended number of holes (thermal vias) in the thermal pad area to ensure optimal thermal transfer.

- Connecting all holes within and outside the thermal pad area to the internal ground plane or other internal copper plane, thus maximizing the thermal dissipation efficiency.

- Employing a direct or solid connection to achieve lower thermal resistance for the internal ground plane, contributing to improved overall thermal performance.

Furthermore, for the bottom copper plane, it is recommended to encircle the vias with a ring of exposed copper (0.05 mm wide) to prevent excessive voiding. This practice, as detailed in the TI Application Report SLOA120–May 2006, ensures optimal thermal transfer and reliability.

QFN Package Stencil Design for Thermal Pad

 To effectively remove heat from the package and maximize electrical performance, it is crucial to solder the die paddle to the PCB thermal pad with minimal voids. Despite potential challenges due to thermal vias and the large size of the thermal pad for larger packages, striving for minimal voids is essential. Furthermore, careful consideration must be given to the reflow process, as out-gassing can lead to defects if the solder paste coverage is too extensive. Therefore, using smaller multiple openings in the stencil for solder paste printing is recommended, as this can result in 50% to 80% coverage, as illustrated in the figure below. While improved coverage generally enhances thermal contact, it's important to be mindful of potential voiding and floating issues in QFN packages.

Thermal Pad Stencil Design for 7mm x 7mm (Left side) and 10 x 10 QFN Packages with 4.9mm and 7.4sq Pads

What is MSL classification?

For packages that are sensitive to moisture, it is important to control the moisture content of the components. Moisture can seep into the package moulding compound from the ambient air, leading to high moisture levels that can damage the package during the reflow process. Therefore, it is necessary to dry moisture-sensitive components, seal them in a moisture-resistant bag, and only remove them from the bag immediately before assembling them to the PCB. The permissible time from opening the moisture-barrier bag until the final soldering process, as well as the duration of exposure to ambient humidity, is specified by the moisture sensitivity level (MSL). The IPC/JEDEC J-STD-033 standard defines eight different MSLs. Information about the MSLs of our products can be found on the "Moisture Sensitivity Caution Label" on the packing material. Additionally, IPC/JEDEC-J-STD-20 specifies the maximum reflow temperature that must not be exceeded during board assembly.

If moisture-sensitive components have been exposed to ambient air for longer than the specified time for their MSL, or if the humidity indicator card indicates excessive moisture after opening the dry package, the packages must be baked before the assembly process. Baking a package too often can cause solderability problems due to oxidation and/or intermetallic growth. It's important to note that the packing material may not be able to withstand the baking temperature, so it's essential to check imprints/labels on the packing for the maximum temperature. Depending on the reflow peak temperature, two levels of moisture sensitivity may be given. Tin-lead devices with a lower reflow peak temperature may withstand a longer soaking time, while lead-free devices with a higher reflow peak temperature may have a derated MSL.

Below is an example of the MSL classification as seen on a Microchip datasheet.

Low drop LDO for Standby Power

 

Introducing the STLQ50, a BiCMOS linear regulator built for environments requiring ultra-low power consumption. With an extensive input range of 2.3 to 12V, it can provide a maximum output current of 50 mA while maintaining an incredibly low quiescent current of 3uA. 

Thanks to the PMOS pass element, it achieves outstanding dropout values (200 mV at 25 mA IO and 350 mV at full load) without compromising consumption characteristics. Housed in the compact SOT323-5L package, it perfectly meets space-saving requirements in battery-powered equipment.

This circuit is a versatile solution for portable/battery-powered equipment, electronic sensors, microcontroller power, and real-time clock backup power applications.