Guidelines for the design and layout of high-speed digital logic PCBs

- Give a lot of consideration to component placement and orientation

- Avoid overlapping clock harmonics. Make a harmonic table for each clock

- The clock signal loop area must be kept as small as possible. Get paranoid about clocks.

- Use multilayer boards with power and ground planes whenever possible.

- All high-frequency signal traces must be on layers adjacent to a plane

- Keep signal layers as close to the adjacent plane layer as possible (<10 mils)

- Above 25MHz PCBs should have two or more ground planes

- When power and ground planes are on adjacent layers, the power plane should be recessed from the edge of the ground plane by a distance equal to 20 times the spacing between the planes

- Bury clock signals between power and ground planes whenever possible.

- Avoid slots in the ground plane. This also applies to the power plane.

- If a segmented power plane is necessary, signal traces must not be routed over the slots.

- Filter (series terminate) the output of clock drivers to slow down their rise/fall times and to reduce ringing typically 33 to 70 ohms

- Place the clock & high-speed circuitry as far away from the I/O area as possible.

- Use a minimum of two equal values decoupling capacitors on DIP packages and four on square packages. On high frequency/ high power/noisy IC many more capacitors may be necessary

- Consider using embedded capacitance PCB structure for decoupling on h-f boards (>50 MHz)

- Use impedance-controlled PCB layout technique with proper terminations where necessary

- On impedance-controlled PCB, do not transition the signal from one layer to another unless both layers are referenced to the same plane

- On non-impedance-controlled PCBs, when a clock transitions from one layer to another & the layers are referenced to different planes add a transfer via or capacitor between the planes

- All traces whose length (in inches) is equal to or greater than the signal rise/fall time (in nanoseconds) must have provision for a series-termination resistor (typically 33 ohms)

- Simulate all nets whose length (in inches) is equal to or greater than the signal rise/fall time (in ns)

- Connect logic ground to the chassis (with a very low Z connection) in the I/O area. This is crucial!

- Provide an additional ground-to-chassis connection at the clock/oscillator location.

- Additional ground-to-chassis connection may also be required

- Daughter boards (with h-f, noisy devices, and/or external cables) must be properly grounded to the motherboard and/or chassis (do not rely on the ground pins in the connector to provide this ground)

- Provide C-M filters on all I/O lines. Group all I/O lines together in a designated I/O area of the PCB

- Shunt capacitors used in I/O filters must have a very low impedance connection to the chassis.

- Use a power entry filter on the DC power line (both C-M and D-M)

- Most products in plastic enclosures need to be provided with an additional metal reference plane

- Consider the use of board-level component shields where applicable

- Ground all heat sinks

Bypass, Decoupling Caps Selection for Voltage Regulators

Bypass Capacitors
The main function of the bypass capacitor is to create an AC shunt to remove undesirable energy from entering susceptible areas.  The bypass capacitor acts as a high-frequency bypass source to reduce the transient circuit demand on the power supply unit. Usually, aluminum or tantalum capacitor is a good choice for bypass capacitors, their value depends on the transient current demand on the PCB, but it is usually in the range of 10 to 47 uF. Larger values are required on the PCB with a large number of integrated circuits, fast switching circuits, and PSUs and having long leads to the PCB.

Decoupling Capacitors
During active device switching, the high-frequency switching noise created is distributed along the power supply lines. The main function of the decoupling is to provide a localized source of DC power for the active devices, thus reducing switching noise propagating across the board and decoupling the noise to the ground.

Ideally, the bypass and decoupling should be placed as close as possible to the power supply inlet to help filter high-frequency noises. The value of the decoupling capacitor is approximately 1/100 or 1/1000 of the bypass capacitor. For better EMC performance, decoupling capacitors should be placed as close as possible to each IC, because trace impedance will reduce the effectiveness of the decoupling function.

Ceramic capacitors are usually selected for decoupling; choosing the value depends on the rise and fall times of the fastest signal. For example, with a 33 MHz clock frequency, use 4.7nF to 100nF, with a 100 MHz clock frequency use 10nF.

Apart from the capacitance value when choosing the decoupling capacitor, the low ESR of the capacitor also affects its decoupling capabilities. For decoupling, it is preferable to choose capacitors with a ESR value less than 1 ohm.

Logic Inverter with Schmitt Trigger

This circuit can take noisy active low input signal, invert the logic and provide clean Schmitt Trigger output.

Soft-Start and Protection Circuit

When the input is below 18 V, Q1 is OFF state allowing C3 to be charged though R3. Thus turning on Q105. Once the input voltage exceed 18 plus two diode drop Volts, Q1 will turn on that discharge C3 and Q105 is OFF.

Once the input goes back below 18 V, Q1 is turn off again. This allows C3 to be charged slowly resulting soft-start at the output.

Pulse Width Stretcher using 555 Timer IC

This circuit will invert and stretch the short period active low input signal as below.

Required pulse width can be calculated by using this equation.

Micro-controller Output Protection by Current Limiting

Q1B is the pass or output transistor. R2 sense the output current. Q1A  is the protection transistor which turns on as soon as the voltage across R2 becomes about 0.65 V.
Maximum current = VBE,Q1A / R2 = 0.65 / 33 = 19.7 mA

High Voltage Monitoring/ Measuring using Microcontroller's ADC input

A voltage divider resistor network could be used for stepping the monitored voltage down to the range necessary for A/D conversion. A passive low-pass filter is used for noise rejection.

Voltage Doubler Circuit

This circuit will convert AC voltage to large DC output voltage. It will take AC input, convert it to DC, and double the voltage to the output.

Reverse Polarity Protection

VGS (th), Gate Source threshold voltage = -2.0 V
Zener Voltage = 10 V, Q1-VGS max = +/- 20V 
Zener diode, D3 will protect the gate from excessive voltages/ unwanted spikes

By referring the Gate signal to the ground line, the device is fully turned on when the battery is applied in the right polarity. For the first start-up, the intrinsic body diode of the MOSFET will conduct, until the channel is switched on in parallel. The Zener diode will clamp the Gate of the MOSFET to its Zener voltage and protect it against overvoltage. By reverse polarity, the MOSFET will be switched off, because the Gate Source voltage for this case will be positive (voltage drop over the Zener diode). 

Logic Input/ Push Button input Buffer Circuit

This circuit squares up and debounces a push button or logic input signal.

Bi-directional Logic Level Shifter

VGS (th) = 1.3 V (Threshold Voltage)
Input = 0V ; VGS > VGS(th) ; FET = ON ; Output = 0V
Input = 3.3V ; VGS < VGS(th) ; FET = OFF ; Output = 5V

A simulation of the above circuit can be seen in the YouTube video link.

Protecting microcontroller Inputs and outputs

1) Filtering

This circuit can be used to protect the I/Os of microcontrollers/ processors.  D1A is used for Transient Voltage Suppression or ESD protection. R1 acts as a current limiting resistor as well as a low pass filter together with C1. The value of the resistor and the capacitor must be sized so that the microcontroller does not miss any signals.

The rise time of the fastest income edge = 2.2 RC

2) Limiting Current

This circuit limit the input current to 23.2 mA (VZ/R1 = 5.1 / 220).

3) Limiting Voltage

Use Schottky diodes with 0.2 Vf for better performance. Once the voltage at the I/O pin is greater than VCC by about 0.2V, the top diode will start to conduct. The bottom diode will conduct for a voltage less than -0.2V.