A Basic Transistor Amplifier with self-bias

This circuit will amplified the input signal with self-bias or feedback which can prevent amplitude distortion. However, it has two small drawbacks. It is only partially effective and, therefore, is only used where moderate changes in ambient temperature are expected.It reduces amplification since the signal on the collector also effects the base voltage. This is because the collector and base signals for this particular amplifier configuration are 180 degrees out of phase (opposite in polarity) and the part of the collector signal that is fed back to the base cancels some of the input signal. This process of returning a part of the output back to its input is known as DEGENERATION or NEGATIVE FEEDBACK. Sometimes degeneration is desired to prevent amplitude distortion (an output signal that fails to follow the input exactly) and self-bias may be used for this purpose.

Common Mode and Differential Mode Filters to limit EMI Issues

This EMI filter include common-mode filter and differential mode filter. Generally Differential mode filter filters noise less than 30MHz and Common mode filter filers noise from 30 MHz to 100 MHz. Both filter have an effect on the entire frequency where EMI needs limiting.

Simple Logic Gates using Diodes

Diodes can be used for implementing simple logic gates such as AND or OR combinations. For AND gate, all inputs must be tie to high, 5V for the output logic high. For OR gate, the output is high if any input(s) are high.

Emergency Phone Charger From 3 x AA Battery with output Protection

Three AA batteries (3 x 1.5V) is using as emergency power source for mobile device or phone charging. Output current is limited to 0.5A and protected from out short circuit or high current drawn from the batteries.

Guidelines for the design and layout of high-speed digital logic PCBs

- Give a lot of consideration to component placement and orientation

- Avoid overlapping clock harmonics. Make harmonic table for each clock

- Clock signal loop area must be kept as small as possible. Get paranoid about clocks.

- Use multilayer boards with power and ground planes whenever possible.

- All high frequency signal traces must be on layers adjacent to a plane

- Keep signal layers as close to the adjacent plane layer as possible (<10 mils)

- Above 25MHz PCBs should have two or more ground planes

- When power and ground planes are on adjacent layers, the power plane should be recessed from the edge of the ground plane by a distance equal to 20 times the spacing between the planes

- Bury clock signals between power and ground planes whenever possible.

- Avoid slot in ground plane. Also applies to power plane.

- If a segmented power plane is necessary, signal traces must not be routed over the slots.

- Filter (series terminate) the output of clock drivers to slow down their rise/fall times and to reduce ringing typically 33 to 70 ohms

- Place the clock & high speed circuitry as far away from I/O area as possible.

- Use a minimum of two equal values decoupling capacitor on DIP packages, four on square packages. On high frequency/ high power/noisy IC many more capacitors may be necessary

- Consider using embedded capacitance PCB structure for decoupling on h-f boards (>50 MHz)

- Use impedance-controlled PCB layout technique with proper terminations where necessary

- On impedance-controlled PCB, do not transitions the signal from one layer to another unless both layers are referenced to the same plane

- On non-impedance-controlled PCBs, when a clock transitions from one layer to another & the layers are referenced to different planes add a transfer via or capacitor between the planes

- All traces whose length (in inches) is equal to or greater than the signal rise/fall time (in nanoseconds) must have provision for a series-termination resistor (typically 33 ohms)

- Simulate all nets whose length (in inches) is equal to or greater than the signal rise/fall time (in ns)

- Connect logic ground to the chassis (with a very low Z connection) in the I/O area. This is crucial!

- Provide for an additional ground to chassis connection at the clock/oscillator location.

- Additional ground to chassis connection may also be required

- Daughter boards (with h-f, noisy devices and/or external cables) must be properly grounded to the motherboard and/or chassis (do not rely the ground pin s in the connector to provide this ground)

- Provide C-M filters on all I/O lines. Group all I/O lines together in a designated I/O area of PCB

- Shunt capacitors used in I/O filters must have a very low impedance connection to chassis.

- Use a power entry filter on the dc power line (both C-M and D-M)

- Most products in plastic enclosures need to be provided with an additional metal reference plane

- Consider the use of board level component shields where applicable

- Ground all heat sinks

Bypass &amp; Decoupling Caps Selection for Voltage Regulators

Bypass Capacitors
The main function of the bypass capacitor is to create an AC shunt to remove undesirable energy from  entering susceptible areas.  The bypass capacitor is acting as a high frequency bypass source to reduce the transient circuit demand on the power supply unit. Usually, aluminium or tantalum capacitor is a good choice for bypass capacitors, its value depends on the transient current demand on the PCB, but it is usually in the range of 10 to 47 uF. Larger values are required on the PCB with a large number of integrated circuits, fast switching circuits, and PSUs and having long leads to PCB.

Decoupling Capacitors
During active device switching, the high frequency switching noise created is distributed along the power supply lines. The main function of the decoupling is to provide localised source of DC power for the active devices, thus reducing switching noise propagating across the board and decoupling the noise to ground.

Ideally, the bypass and decoupling should be placed as close as possible to the power supply inlet to help filter high frequency noises. The value of decouupling capacitor is approximately 1/100 or 1/1000 of the bypass capacitor. For better EMC performance, decoupling capacitors should be placed as close as possible to each IC, because trace impedance will reduce the effectiveness of decoupling function.

Creamic capacitors are usually selected for decoupling; choosing the value depends on the rise and fall times of the fastest signal. For example, with a 33 MHz clock frequency, use 4.7nF to 100nF, with a 100 MHz clock frequency use 10nF.

Apart from the capacitance value when choosing the decoupling capacitor, the low ESR of the capacitor also affects its decoupling capabilities. For decoupling, it is preferable to choose capacitors with a ESR value less than 1 ohm.

Logic Inverter with Schmitt Trigger

This circuit can take noisy active low input signal, invert the logic and provide clean Schmitt Trigger output.

Soft-Start and Protection Circuit

When the input is below 18 V, Q1 is OFF state allowing C3 to be charged though R3. Thus turning on Q105. Once the input voltage exceed 18 plus two diode drop Volts, Q1 will turn on that discharge C3 and Q105 is OFF.

Once the input goes back below 18 V, Q1 is turn off again. This allows C3 to be charged slowly resulting soft-start at the output.

Pulse Width Stretcher using 555 Timer IC

This circuit will invert and stretch the short period active low input signal as below.

Required pulse width can be calculated by using this equation.

Micro-controller Output Protection by Current Limiting

Q1B is the pass or output transistor. R2 sense the output current. Q1A  is the protection transistor which turns on as soon as the voltage across R2 becomes about 0.65 V.
Maximum current = VBE,Q1A / R2 = 0.65 / 33 = 19.7 mA

High Voltage Monitoring/ Measuring using Microcontroller's ADC input

Voltage divider resistor network is used to step monitored voltage down to the range as necessary  for A/D conversion. Passive low-pass filter is used for noise rejection.