Showing posts with label EMI. Show all posts
Showing posts with label EMI. Show all posts

Thursday, April 23, 2026

EMC by Design - Systematic Approach (Emission Control - Line Termination)

     





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EMC by Design - Systematic Approach (Emission Control - Components & Circuits)

 

Frequency Sprectra for Various waveform
Harmonic envelop of trapezoid

Comparison of harmonic Spectra of logic families
Recommeded design practice at component level



Recommended design practices at component level continue

Recommended design practices at circuit level

Allowable loop area for various logic family
Allowable track length for vairous logic family



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EMC by Design - Systematic Approach (PCB Layer Stack up)

 

PCB Layer stack up Guide for Multi-Layer PCB
PCB Layer stack up for 4 layer stack up with illustration
Low cost 4 layer stack-up with embedded capacitance and Intel's recommendation




Symmetrial six-layer PCB stack-up
Equally spaced 6 Layer PCB stack-up
Symmetrical Eight-layer PCB Stack-up
Symmetrical Eight-layer PCB stack-up




Design Rule for Ground Layout

Recommended practive for Layout & Grounding


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EMC by Design - Systematic Approach (Grounding - Signal Reference Ground, 0V)

 

Diagram illustrating single point grounding for analog, digital, and high power loads, showing current paths to power supply in two different grounding configurations.
Diagram showing a modified single-point grounding system with analog, digital, and analogue inputs connected to low-power and high-power outputs.

ALT Text: Diagram illustrating the grounding signal reference ground (0V) with four types of signals—Analog, Digital, High Power Loads, and Power Supply—each connected to a common grounding point through separate current paths labeled I1, I2, I3, and I4. The diagram emphasizes the limitation of single-point grounding systems.
The diagram depicts the impedance of a grounding system with long ground wires, including equipment connections, an equivalent circuit featuring inductance and capacitance, and a graph showing impedance variations with frequency highlighting parallel and series resonances.
Diagram showing impedance and resonance in grounding system circuits and printed circuit tracks.





Diagram of a grounding system showing signal reference ground (0V) with connections for analog, digital, high power loads, and power supply, all connected to a ground grid with current paths labeled I1 to I4.













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EMC by Design - Systematic Approach (Circuit Layout - Chassis Bonding)

   

EMC by Design - Systematic Approach (Circuit Layout - Chassis Bonding)
EMC by Design - Systematic Approach (Circuit Layout - Chassis Bonding)

Chassis bonding reduces Transfer Impedance
Closer PCB - Chassis spacing results in lower emission

Circuit layout - Chassis Bonding Rule

PCB - Chassis Bond - Side and Plane View

PCB - Chassis Bond Layout Options

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EMC by Design - Systematic Approach (Emission Control - Decoupling)

 

Noisy current emit magnetic fields and noisy voltages and emit electric fields
Need for decopuling due to cause of fluctuating currents
Achieving low suppy impedance over the frequency range
Time-domain view of power supply decoupling
Every power pin needs local decoupling. An exammple of a PCB with 0V adn power planes with decoupling capacitors placement with via connection to GND and power planes.
a technical illustration detailing the concept of decoupling on a Printed Circuit Board (PCB) with a 0V plane. The diagram shows an integrated circuit (IC) and a decoupling capacitor (decap) connected to a power trace carrying DC power. Key design principles are highlighted, such as the power trace passing through the decap's pad before connecting to the IC, and the decap and IC power pin sharing the same pad with minimal distance. Vias to the 0V plane are illustrated, emphasizing direct connection for minimum impedance
This is a technical diagram that shows "Emission Control - Decoupling" and "Minimizing decap's connection inductance." The diagram displays a printed circuit board (PCB) layout with an integrated circuit (IC) and a decoupling capacitor (decap). It emphasizes the decap's position relative to the 0V plane and the power plane, noting that for best results, the decap should be put as close to its corresponding power or ground pin on the IC. The diagram also depicts DC power traces, a small power plane, the PCB's edge, and the 0V plane. Text annotations give directions for connecting both the IC and decap directly to the 0V and power planes utilizing minimum length pin-escapes and break-outs, and only using thermal break pads.


This presentation, labeled 'Emission control - Decoupling' and with the 'Series resonance in decoupling capacitors' subtitle, provides a graph displaying the impedance (Zeff in Ω) vs frequency (MHz) for several types of MLCC (Multilayer Ceramic Capacitor). The graph compares ideal and actual capacitors, taking into account connection inductance and ESL. It emphasizes the concept of self-resonant frequencies (SRFs) for 100nF, 10nF, and 1nF MLCCs.
Circuit layout showing an example of decoupling capacitor placement with soft ferrite suppressor bead as a filter for power supply
WHen thre are few decaps on a power plane, they should all have the same value. PCB layout illustration for power planes islands fed by pi filters with ferrites.
An examples of PCB layout showing poor and good placemnt of parallel capacitors
Using three parallel decoupling capacitors with different values is a traditional engineering practice designed to target power supply noise across a wide frequency spectrum. The math dictating parallel networks confirms that total capacitance is simply the sum of all parts:
Flux cancelFlux cancellation is a PCB layout technique that minimizes decoupling capacitors' Equivalent Series Inductance (ESI) by routing currents so that their magnetic fields oppose and cancel each other out. Because a capacitor's high-frequency effectiveness is severely restricted by its loop inductance, flux cancellation is essential in high-speed digital circuits.
An X2Y attenuator component is a specialised, four-terminal Multi-Layer Ceramic Capacitor (MLCC) internal circuit structure engineered to drastically lower Equivalent Series Inductance (ESL) through advanced internal flux cancellation. While a standard MLCC consists of opposing layer pairs, an X2Y device embeds a third set of internal shield layers that isolate and wrap around the standard electrodes, creating an integrated three-node capacitive circuit














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